Multiple bus architectures operating within multiple processor system environments have become more common. In such systems, bus interfaces or bridges field transactions from one bus and forward the transactions onto another bus.
The bus interface normally sends acknowledgement signals to a bus after accepting a transaction. FIG. 1 illustrates a situation in which there are two distinct bus domains and immediate address acknowledgement. In the specific example shown, a master device (not shown) in a processor bus domain 12 is attempting to read data out of a slave or target device 16 in a second bus domain 14 (such as a PCI bus) across a bus boundary indicated by the dashed line. In order to perform this read operation, the master device transmits a read access request addressed to the target device 16 via a bus interface 18. The bus interface 18 issues an address acknowledge signal to the processor bus 12 immediately upon receipt of the read access request and then forwards the read access request on to the target device 16. Upon receiving the acknowledge signal, the master device waits for the target device 16 to send the requested data back via the bus interface 18.
In the second bus domain 14, if the target device 16 is presently capable of complying with the read access request, it does so by sending the back the requested data. However, if the target device 16 can not accept the read access request upon receipt, the bus interface 18 will continue to retry the read access in the second bus domain until the target device 16 finally accepts it. The second bus target retries, however, cannot be communicated back to the first processor domain 12 because the first bus is waiting for the read data from the target device 16 and cannot allow more than one transaction to occur at a time. This can lead to other accesses being blocked.